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Lattice Semiconductor
Functional Description
Aborted Transmission Due to FIFO Empty - Tx MAC Application Interface
If the tx_fifoempty is asserted while the Tx MAC is in the process of reading a frame, the MAC will stop reading the
frame and assert tx_disfrm to indicate an erroneous transmission. The frame transmission is abandoned when this
occurs. Note in Figure 2-14 the tx_fifoempty was asserted before the end of the frame (no tx_fifoeof asserted).
Figure 2-14. Aborted Transmission Due to FIFO Empty
txmac_clk
tx_fifoavail
tx_fifodata[7:0]
1
2
62
63
64
tx_macread
tx_staten
tx_staten[31:0]
Valid
tx_fifoeof
tx_fifoempty
tx_discfrm
tx_done
Reception and Transmission of 64-byte Frames With SGMII Easy Connect Option
Figure 2-15 and Figure 2-16 illustrate how clock enables are used on the MAC client interface when the MAC is
configured with SGMII Easy connect option. Note: the SGMII PCS IP sources the appropriate clock enables to the
MAC. For one Gbps operation the clock enables are always high, for 100 Mbps operation the clock enables are
asserted high once every 10 (125 Mhz) clock cycles, and for 10 Mbps operation the clock enable is asserted high
once every 100 (125 Mhz) clock cycles.
Figure 2-15. Transmission of a 64-byte Frame at 100 Mbs Data Rate
tx_clk_en
sys_clk_125
tx_macread
tx_fifoeof
tx_fifodata[7:0]
IPUG51_03.0, December 2010
1
34
2
64
Tri-Speed Ethernet MAC User’s Guide
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